The present invention relates to the field of digital logic circuits and, in particular, relates to improved multiplexer circuits.
Known multiplexer circuits are built up of a binary tree arrangement of "one-of-two" or 2-input multiplexer circuits. For N input variables, a first stage (or input stage) comprises N/2 2-input multiplexers, arranged in parallel to receive the input variables. Each stage reduces the number of signals in half, so each stage requires half as many 2-input multiplexers as the preceding stage. The final stage (or output stage) selects one of two remaining signals as the output signal.
To illustrate, a known 8-input or 8:1 multiplexer circuit comprises an input stage having four 2-input multiplexer circuits arranged in parallel to receive the input variables and provide four output signals. A second stage comprises two 2-input multiplexer circuits arranged in parallel to reduce the four first-stage output signals to two output signals. A final stage 2-input multiplexer selects one of the two output signals as the multiplexer output signal.
In the prior art, all of the multiplexers in each stage are controlled by a corresponding binary control signal. Thus, prior art multiplexers have log.sub.2 stages, and have log.sub.2 control (or select) inputs, for selecting one of the input variable signals. Examples of known multiplexer circuits are shown in the TC19G000 Macrocell Data Sheet at pages 1-109 (mux 4 cell) and 1-110 (mux 8 cell) (1986).
One disadvantage of known multiplexers is loading on the control inputs. The control inputs must drive all of the multiplexer circuits in a stage, which may be, for example, 8 or 16 muxes in the first stage. This can lead to undue delay in controlling the circuit.
Another limitation inherent in the prior art approach is the use of log.sub.2 control (or select) lines. This requires binary encoding the desired selection. A greater number of select lines could be used to simplify such encoding.
It is also known in the prior art to arrange a pair of transmission gates so as to form a 2:1 multiplexer circuit. Each of the transmission gates comprises a pass transistor or a complementary pair of transistors, such as a CMOS pair. Usage of various forms of transmission gates in logic circuitry is disclosed in applicant's U.S. Pat. No. 5,040,139 and referenced cited therein.